Common Questions

Features and other tech questions

CF_Q1: What format of netlist file is accepted?
CF_A1: All software support Cadence (OrCAD) Capture exported plain Allegro format netlist file. When generating netlist file, switch to 'Other' tab, choose ALLEGRO as Formatter.
ALLEGRO.DLL may be unavailable in higher versions, please use telesis.dll or orTelesis.dll instead.
Products also supporting Altium Design and ConceptHDL Concise formats:
	ACompare V1.1.0.0 and later;
	BSTest V2.2.1.1 and later;
	PinLock V1.1.0.0 and later;
Products also supporting PADS formats:
	ACompare V1.1.0.1 and later;
	BSTest V2.4.0.0 and later;
	PinLock V1.1.0.1 and later;
Products also supporting PADS formats:
	ACompare V1.1.1.0 and later;
	BSTest V2.9.2.0 and later;
	PinLock V1.1.1.0 and later;

CF_Q1_A: What's a netlist file?
CF_Q1_A: In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. A network (net) is a collection of two or more interconnected components. 
Netlist file is exported by EDA tool from schematic or PCB.

CF_Q2: The software always said 'No cable detected'. I have tried other cables, but still the same result.
       Or, you are told 'The ordinal xx could not be located in the dynamic link library FTD2XX.dll'.
CF_A2: Following bellow steps:
 1, Quit the software;
 2, From 'Device Manager', uninstall the 'USB Serial Converter' device and remove installed driver;
 3, Disconnect the cable from your computer;
 4, Run CDMxxxxx_Setup.exe (xxxxx stands for version number) in the installation package to re-install driver; Please note: If the OS is Windows Vista/7/8 or later version, please run installation as administrator;
 5, Connect the cable to your computer;
 6, Launch the software again;

CF_Q3: I need to run different batch operations in different workspace file. How to do?
CF_A3: If the workspace files could be merged to one file, it's obviously an answer.
But, there should be some difference between the files (for example, different cable clock frequency, also it may happens to different board or different JTAG port on one board), so merge may not work.
We suggest you to use command line parameter (/workspace) when running loader.exe to tell the software which workspace file should be loaded when startup.
Please note: We were told some customers are using another solution: to copy the software to several folders, and use the different default workspace file under each folder. They did the job with launching software form different folder. It is NOT recommended.
Besides, with command line parameter, you could use workspace files which are not located at the same folder as the software. This means you may any filename beside specified workspace filename (e.g. BSTest.ini or yaJFPb.ini) to implement auto run actions and quit silently.

CF_Q4: JTAG operation is not stable, and the signal quality is bad. Any suggestion?
CF_A4: Please follow these instructions:
1, Slow down TCK frequency following the software user guide;
2, Disconnect all pins of cable from target board, and measure the signal on the cable. If the signal quality is still bad, maybe there's something with the cable, please buy a new one. If the signal quality is good now, the cause is the target board. Please check and fix it.
3, Also you can adjust driving current with CableUpdate utility.
   3.1 Default current of cables shipped before 2015/9/11 is 4mA, please adjust to 8mA or 12mA if the JTAG signal level is too low;
   3.2 Default current of cables shipped after 2015/9/11 is 12mA, please adjust to 8mA or 4mA if the JTAG signal has reflection or steps;

CF_Q5: The AutoRun feature of the software is wonderful! But, the command line return immediately after I type xxx.exe. Is it possible to return back to command line prompt till the software finishes its job?
CF_A5: Yes, please use 'start /wait xxx.exe' to call the software under command line window.

CF_Q6: What's the difference between different run modes?
CF_A6: The software could be launched in several ways:
1, Normal mode. Double click 'loader.exe' in Windows explorer or run 'loader.exe' from command line. The software will search default workspace file (e.g. yaJFPb, BSTest.bst) and load configuration, and run preset operation if AutoRun is specified. The software will stay on GUI.
2, Parameter mode. You can create a shortcut with parameter then double click the shortcut, or run 'loader.exe /workspace:workspace_filename'. The software will load workspace file named workspace_filename and do same things as 'Normal mode' listed above.
3, PseudoCLI mode. Run 'start /wait yaJFPb.exe workspace_filename' from command line. It's designed for unattended operation. The software will run preset AutoRun operation specified in workspace file named workspace_filename then quit automatically. The caller could fetch return code form %errrorlevel%.

CF_Q7: I changed the TCK frequency in workspace file on PseudoCLI mode, but the software crashed in splash screen.
CF_A7: The 'Crash' is caused by failure when checking JTAG ID, so later operation will not be launched. It's a normal behavior. You may check this by log file.
The highest frequency could be found by 'jscan' program. Please do not set TCK at higher frequency than supported.

CF_Q8: What kind of connector is used on board to connect with JTAG cable?
CF_A8: To support as more JTAG devices as possible, JTAG cable uses DuPont line to connect with target board. If your target connection is fixed, user can use specified adapter board to speed up connection.

CL_Q1: What's the form of license?
CL_A1: Node-Locked license file. One license could only be used on one given computer.

CL_Q2: Could the license be transferred from one computer to another?
CL_A2: It depends on the license type. There are two types of license: Hardware-Bound and Hardware-Not-Bound. A company could only choose one type of licenses.
Here is the difference:
	License is not bound with cable. Cables could be exchanged between computers.
	License transfer is not allowed.
	A cable could be used only on one given computer.
	The license could be transferred once max free of charge when license is valid.

CL_Q3: Why did my software say license check failure?
Situation 1:If you didn't change the computer hardware, maybe one of your physical network adapter card was disabled.
Solution: Enable it.
Note: Sometimes, especially on Windows 7 and later OS, a network adapter card will be disabled automatically if its link keeps down for a period of time. If this happens, you must enable it manually. For your convenience, you may keep the link up, and Internet access is optional. But an active Internet access will accelerate the startup of software.

Situation 2: Windows system issue.
Solution: Uninstall NIC driver and re-install it.

CL_Q4: My computer could not access Internet. Does it matter?
CL_A4: For your convenience, our software doesn't require your computer to have Internet access. But an active Internet access will accelerate the startup of software.
Note: Please keep all network adapters are enabled.

CL_Q5: The software could not start after installing virtual machine.
CL_A5: Earlier version software may fail when getting hardware id if a virtual machine is is installed.
BTW, some VPN client software will add virtual NIC to your computer when installing the VPN client.
Workaround: Disable virtual network adapter card.
Recommended Solution: Please contact us to get a latest copy.

CL_Q6: I didn't touch the license file, but I am told license error and error code is 4.
CL_A6: The hardware/software identification of your computer has changed. If you are sure to have obeyed the 'License Agreement' and your requirement meets the contract, please follow instruction in the install guide to obtain a new license.

CL_Q7: Is my license still valid after I re-install Windows on the computer?
CL_A7: It depends:
If the hardware does not change, the software will think it's the same computer, so the license still works.
If part of hardware changes, please contact us. We'll check and send you a new license if it really is the original computer.
If no hardware info matches with original computer, or the hardware info differs too much to judge whether they are the same computer or not, we'll think it's a new computer, and you must buy a new license.

CL_Q8: Could the products with certain postfix(-S, -L, -P and -U) be upgraded to another one?
CL_A8: You may pay for additional features, but you could not prolong license validation.
For example: You may upgrade from postfix -S to -P, and from postfix -L to -U, but you could upgrade from postfix -S to -L or -U, nor -P to -U.

CM_Q1: I could not see attachment when receiving your mail.
CM_A1: This happens when your mail server scans every attachment of arriving mail. The sever remove the attachment if the file comes with an extension marked to be deleted, e.g. exe.
Solution: Please let us know and we'll re-send a copy to you. We'll encrypt the file names in the archive. The mail server will let the attachment pass.

CM_Q2: Could I put all files of all software at the same folder?
CM_A2: Sure. You'll be asked which program you want to launch when loader.exe is starting.
For your convenience, it's suggested to leave files of different software at different folder.
If you insisted put all software under the same folder, and you don't like to select every time, you may run loader.exe with a command line parameter (/loader) to launch corresponding software.
And license file is required to be at the same folder at the program file. //In fact, license file may be placed at anywhere else. For the same reason, i.e., for your convenience, please let them be together.

CM_Q3: What's difference between renewal and not renewal after free support is expired?
CM_A3: After free support period is expired (To most products, it's one year. For detailed info please check product specification and the contract), you may choose renewal or not renewal.
If no renewal, tech support is limited to public documents and FAQs on our website.
If renewal, tech support will also include telephone, Email or IM (Just the same as free support described in the product specification and the contract).


BST Pre-sales FAQs

TP_Q0: I want to know whether there is any short-circuit or open-circuit issue on my board easily. How? And sometimes I could not observer pin status of a BGA pin without any via or trace. Any good ideas?
TP_A0: Our software will solve these problems. The software could detect manufacturing issues, and can be used as a debug tool. It can display status of JTAG chip's pins (something like an oscilloscope or logic analyzer). Also the software can act like a signal generator by controlling the chip to output a user defined waveform.
Besides this manual testing mode, the software could run a single chip automatic test to find short-circuit issues.
Furthermore, if there are more than one devices in the JTAG chain, the software could detect short-circuit and open-circuit issues of the inter-connection signals.
For more info, please read White Paper: Test.

TP_Q1: What's period of output signal?
TP_A1: First, it depends on the BOUNDARY_LENGTH of JTAG device. The bigger BOUNDARY_LENGTH results in longer JTAG operation cycle.
Second, it depends on the cable. It will be 10x times faster than parallel cable when programming with WH-USB-JTAG cable; 5x times faster than WH-USB-JTAG with WH-USB-HiJTAG.
An example: BOUNDARY_LENGTH = 539, WH-USB-JTAG cable, looping refresh, the period is less than 1ms.

TP_Q2: Can BST software configure a CPLD?
TP_A2: Yes, theoretically.
The software could process .svf and .vme (Version 12.2) file.
So, no matter the CPLD vendor is Altera, Xilinx or Lattice, if you have .svf or .vme file, you can use our software to configure your CPLD.
OK, why .svf? Because some vendors keep their programming file format as a secret (e.g. Altera's .pof file), so we don't know how to read. Meanwhile, .svf is an open standard format.
Since .svf file could not do a file saving job, so we could not read programming data from CPLD and save data to a file with the software. But, good news is that the 'verify' operation is available if you could provide a .vme or .svf file.
//Our software platform could configure Altera FPGA under 'Passive Serial' mode with .rbf file, and also support configuring Xilinx FPGA under 'Slave Serial' mode with .bit file. Note: Serial configuration mode is NOT JTAG mode.

TP_Q3: What target does 'Peripheral Test' test?
TP_A3: The JTAG device itself is the DUT for Inter-Device Test, Single Device Test and Manual Test. And 'Peripheral Test' will test components connected to JTAG device, typically a Flash.

TP_Q4: What the necessary conditions for JTAG test? 
TP_A4: A JTAG is cable is required by the BSTest software to communicate with your target board.
The JTAG signals of your target board should be accessed, and BSDL file of DUT (Device Under Test) is also required for all tests.
If you plan to run a manual test, the schematic is required.
And if you want to run inter-device test, the netlist file is required.

TP_Q4_A: What's a BSDL file? 
TP_A4_A: Boundary scan description language (BSDL) is a hardware description language for electronics testing using JTAG. It is provided by IC vendor.
BSDL is a VHDL subset. Each BSDL file describes one version of an IC and has many package pin maps as are available for a particular die.

TP_Q5: Will the JTAG test platform support secondary development?
TP_A5: The JTAG platform supports script file for automation and integrating into existing systems.
If you need more powerful and interactive testing interface, please contact us to order the dll package which supports Tcl.
Please note: You could run the Tcl source file in Tcl/Tk shell, also you could run Tcl source file from the console command line.

TP_Q6: BSDL file is necessary to JTAG test, so I could not run JTAG test if I don't have a BSDL file. Is that true? And, can I generate a BSDL file according to the datasheet?
TP_A6: Yes, a JTAG test could not be run without corresponding BSDL file.
You can never generate a BSDL file by yourself. BSDL file is an apparent description of internal JTAG design.

TP_Q7: What's the difference between ICT and JTAG?
On manufacturing:
	ICT is the first procedure after PCB is assembled; JTAG is after ICT and powered on.
	ICT equipment is expensive, and ICT need special device for each PCBA; JTAG only needs JTAG cable connecting to target board and is the same to all PCBA.
	ICT need physical many test points; JTAG uses on physical probe.

On RD and repair:
	ICT is for manufacturing only; JTAG could be used for RD (Flash programming, PLD configuration, etc.) and repair (Test SRAM, Flash device besides PCB assembly).

Please refer to our JTAG training and white papers for test and PLD configuration.

TP_Q8: Could JTAG test figure out whether the device is good or not?
Generally speaking no, because JTAG test works at EXTEST mode, it focuses on soldering and PCB traces.
In detail, JTAG test could check Flash and SRAM attached to JTAG device(DUT), since BSTest software will read and write data to them.
Please refer to our JTAG training and white papers for test and PLD configuration.

TP_Q9: BSTest tests the PCB connection, not internal BIST. Is it right?
Yes, you're right.
EXTEST instruction is mandatory, while INTEST and RUNBIST instructions are optional. And INTEST/RUNBIST will not disclosure to customer.
Please refer to our JTAG training and white papers for test and PLD configuration.
BST After-sales FAQs

TA_Q1: I could see a clock pin toggles. Could the software tell me the frequency of a clock?
TA_A1: No, except the clock frequency is low enough because the software need time to update input value (refer to TP_Q1). We know, to sample a signal correctly, the sampling rate should be at least twice of the frequency of a signal.

TA_Q2: Is it possible to run a batch of tests by one click?
TA_A2: Yes, please update to V2.2.2.0.
Note: A GUI tool called FileHelper in the software package will help you do below job since 2015/1/31.
Create a plain text workspace file (suggested file extension is .bst). Add these lines to the file:
;Set cable frequency to 15MHz;Change 15000000 to what you want. Read the user manual for valid values.
;Set cable clock frequency automatically when startup
;Change these test actions and cfg files to your own.
;Save log to file automatically when exit
;end of workspace file

This workspace will set cable clock to 15MHz, and run 3 tests automatically (use character '|' to split multi tests): two inter-device tests and one single device test.
Two kinds of tests are supported: IDT (Inter-Device Test) and SDT (Single Device Test). Note: Manual Test needs user interaction, so is not supported in batch tests.
Please use character ':' to split action and configuration file. You could save a configuration file at the Test Configuration dialog.

Once you have a workspace file, select main menu Test - Batch Test and choose the workspace file. The software will do all tests listed automatically and show the result.

Furthermore, if valid AutoRun exists in the BSTest.ini file located in the same folder as the software, the software will run all listed tests automatically without clicking any button. If no error happens, the software will quit silently. And the software will break the tests and show you if error happens. This feature will let you easily integrate the software with existing manufacturing automation system.

TA_Q3: Everything is OK when testing the FPGA or CPLD on my board, but random failure happens when testing CPU. Why?
TA_A3: Usually it is caused by the watchdog reset of CPU. Also, failure may happen if pin TRST is not connected with JTAG cable properly.

TA_Q4: What's the difference between 'Workspace File', 'Configuration File' and 'Setting File'?
TA_A4: A 'Workspace File' specifies one or more 'Configuration File' and stores software settings and parameters. While a 'Configuration File' only contains test info (a configuration file may contain one setting file) without software settings or parameters (e.g. TCK Frequency, etc.)
And a 'Device Setting File' contains pins to be tested in a single device test.

TA_Q5: There are two devices in JTAG chain: one TI DSP and one Lattice CPLD. But only CPLD is detected. How to configure TI DSP to use boundary scan?
TA_A5: To some DSPs, you should pull-up both EMU0 and EMU1, for example TMS320VC5420. Its datasheet says: During boundary scan tests, EMU0 and EMU1/OFF must be held high while TRST is transitioned from low to high.
And to some DSPs, you should pull-down both EMU0 and EMU1, for example TMS320C6000. Its datasheet says: When EMU0 and EMU1 are pulled low, then only the boundary scan TAP is in the path, and only boundary scan is possible.
So, it depends on your DSP device.
By the way, if you don't want to change the pull-up or pull-down resistors on your board, you need the boundary scan test software to control EMU0 and EMU1 dynamically. In such a case, you can order an extended JTAG cable with extra EMU0 and EMU1 pins from us.
And set the EMUx pins value in workspace file like this:
;If decimal integer 2 is set, it's 10 in binary, so EMU1 will be 1 and EMU0 will be 0.

TA_Q6: Could I send a PWM signal when running manual test?
TA_A6: Sure. If output pattern is 01, the duty cycle will be 50%. Similarly, pattern 001 gets 33% duty cycle and pattern 011 gets 66% duty cycle.
The frequency could be measured by an oscilloscope since it depends on the JTAG device.
If you want to adjust the frequency, please modify the output pattern. For example, if the pattern is set to 0011, the duty cycle is still 50% but the frequency will be half of pattern 01.

TA_Q7: What happens to JTAG test if FPGA/CPLD is configured? And how about MCU/CPU?
TA_A7: To PLD like FPGA or CPLD, the BSDL file is generated for blank device that is not configured. It's suggested to configure PLD after JTAG test. If you insist on it, please use vendor's EDA tool to generate new BSDL for your configured device.
To MCU/CPU, it's also suggested to program ROM/Flash after JTAG test. If you insist on it, please make sure MCU/CPU could enter JTAG test mode.
In a word: To get better test result and wider test coverage, please keep FPGA, CPLDs blank when testing, and do not program or configure them before test. And please keep CPUs in idle status, i.e. do not program their Boot ROMs or Flashs before test.


JFP Pre-sales FAQs

PP_Q1: How fast does JFP program Flash?
PP_A1: First, it depends on the BOUNDARY_LENGTH of JTAG device. The bigger BOUNDARY_LENGTH result in longer JTAG operation cycle.
Second, it depends on the cable. It will be 10x times faster than parallel cable when programming with WH-USB-JTAG cable; 5x times faster as WH-USB-JTAG with WH-USB-HiJTAG.
Third, it depends on whether the CPU's address buses and data buses are multiplexed or not. If multiplexed, it will be half speed as the CPUs which are not multiplexed.
Fourth, it depends on the write buffer of Flash. Bigger buffer will make programming faster.
Last, it depends on the data bus width.
For example: BOUNDARY_LENGTH=476, Address and Data bus not multiplexed, 16 bit data bus, 32 bytes write buffer NOR Flash, WH-USB-JTAG cable, Speed: 6KiB/s.
Another example: BOUNDARY_LENGTH=2281, Address and Data bus not multiplexed, 16 bit data bus, 32 bytes write buffer NOR Flash, WH-USB-HiJTAG, Speed: 10KiB/s. P.S. The speed will be 2KiB/s if WH-USB-JTAG cable used on the same board.

PP_Q2: What methods are used to programming Flash?
PP_Q2: Please read White Paper: Programming Flash.

PP_Q3: Is my cable supported by the JFP software?
PP_A3: As said, we support Lattice, Altera and Xilinx parallel port cables and our USB cables.
To USB cables of other vendors, MCU or CPLD may be used in the cable circuit. Our software will not support those cables which work with private protocols.
The software support our USB cables and some 3rd party USB cables with open protocols.

PP_Q4: What's Linear BPI Flash?
PP_A4: Linear Flash, is called by Xilinx to distinguish other vendors' Flash with Xilinx own Platform Flash.
Flash 28F256P30 come from Intel/numonyx are used on Xilinx ML50X, ML60X and other reference design boards.
Our software could program these Flash without iMPACT. The more important thing is our software runs up to 10x times faster than iMPACT.

PP_Q5: What are the requirements to program Flash with JFP?
PP_A5: A JTAG cable should be used to connect your target board and computer.
To the target board:
	Hardware: The board must have a JTAG header to connect the cable.
	Files: We need the datasheets of Flash (if the Flash is new and not in built-in Flash list) and the JTAG device.
		When programming Flash with JTAG test mode (yaJFPb works in this mode), BSDL file of JTAG device is required. Also you should know the connection between CPU and Flash, so a schematic is preferred. Besides, if Flash signals are controlled by a CPLD, you should know the control logic.

PP_Q6: What's the advantage of Zhefar solution compared with CodeWarrior + USB TAP?
PP_A6: As far as programming Flash is concerned:
	Much easier to use than CodeWarrior! No initialization of clock/registers/RAMs is needed.
	You can use our software whenever JTAG is accessible even if RCW (Reset Configuration Word) is bad.
	Calculate corresponding Flash blocks/sectors for programming, and could erase them automatically before programming.
	Better performance to price ratio. How much is USB TAP? CWH-UTP-PPCC-HE: USD495. How much is the cheapest CodeWarrior?  CWP-BASIC-NL: USD995. But, if you just want to programming Flash, only about 1/2 cost is enough.
	Faster in most cases.
	Our solution supports ARM/MIPS and other architectures besides PowerPC, and even CPLD/FPGA or any ASIC. Up to 10x faster than iMPACT when programming BPI Flash attached to Xilinx FPGA. (Programming speed depends on Flash, JTAG device and other parameters, and please visit our support webpage for more info.)
	Lightweight green software.
	Support multi devices in JTAG chain.
	Local support. Quick response.
	Customization is supported.
When using for mass production:
	Cost of CodeWarrior+USB TAP is high. While our solution use very cheap cable. More discount when buying more copies.
	Load configuration file automatically when startup.
	Batch programming: Support programming different file to different address.
	Programming many boards just need to launch the software once.
	Easily integrated with manufacturing automation system: Run specified operations automatically and silently without clicking any button.
	Calculating hash value of programming file based on multiple algorithms. Avoid writing wrong file by comparing calculated value with expected value.

PP_Q7: We use 'bootrom+Flash' solution. What will yaJFPb solution benefit?
PP_A7: It's a trend to design without bootrom PLCC socket. Besides,
	1st, Don't need the Flash sockets anymore. Lower cost. Higher reliability.
	2nd, Save PCB area.
	3rd, Don't need to pull out bootrom from socket and go to the programmer to burn bootrom. More efficient. More convenient.
	4th, No need the jumper (0 ohm resistor) in your design, and no soldering when switching between bootrom and Flash.
	5th, When a board is returned for repairing, you have to do some extra work before debugging. With yaJFPb solution, you could read the Flash directly.

PP_Q8: We know there are many success stories from Zhefar's customers. Could you share them?
PP_A8: Below cases are true stories and issues are all solved by Zhefar's yaJFP solution.
	The Flash is welded after burning data, but unfortunately wrong data is programmed so the board is 'bricked';
	RCW (Reset Configuration Word) data in Flash is bad, so emulator could not connect to the target board;
	Emulators are very expensive and easily destroyed if used frequently;
	Every CPU of different architecture needs one kind of emulator;
	BootRom is stored on a PLCC package Flash, and engineers must dig it from the socket before programming;
	Embedded software development environment is too huge and too hard to use, so it's not suitable for manufacturing;
	Welding issues happened to SDRAMs, and emulator could not connect to the target board;
Zhefar's yaJFP(Yet Another JTAG Flash Programmer) software supports CPU based on PowerPC(PPC)/MIPS/ARM and other architecture, and DSPs, CPLDs and FPGAs from any vendor are also supported. Besides, it's a lightweight green software and very easy to use.

PP_Q9: What hash algorithm does yaJFP support for programming file?
PP_A9: To avoid writing wrong file, yaJFP will compare expected hash value(specified in workspace file) and calculated value. Supported algorithm and result format are listed below: (The hash result is a hexadecimal string in lower case, having no space or '0x')
Sum: Add every byte of programming file as unsigned integer, and output 8 digits hex char(add leading zero when necessary);
CRC32: 8 digits hex char;
GOSTHash: 64 digits hex char;
MD2: 32 digits hex char;
MD4: 32 digits hex char;
MD5: 32 digits hex char;
SHA-1: 40 digits hex char;
SHA-2 256: 64 digits hex char;
SHA-2 384: 96 digits hex char;
SHA-2 512: 128 digits hex char;

PP_Q10: Does yaJFPb support SPI Flash?
PP_A10: yaJFPb does not support SPI Flash, while yaJFPs does.
Both products use the same cable.
The difference is: yaJFPb controls CPU's JTAG pins to program parallel interface Flash, while yaJFPs controls SPI Flash's pins directly.

PP_Q11: Could yaJFPb be used to program MCU internal Flash?
PP_A11: No. Because yaJFPb could access external Flash with standard JTAG instructions, while programming internal Flash needs vendor's private protocol which is not publicly available.
JFP After-sales FAQs

PA_Q1: Pending.
PA_A1: Pending.

PA_Q2: Pending.
PA_A2: Pending.

PA_Q3: Flash xxxx Manufacture Code should be 0xXX, but 0x0000 read.
PA_A3: Possible reasons:
    PA_A3.1  Flash is not powered. Check power supply.

PA_Q4: Flash xxxx Manufacture Code should be 0xXX, but 0xFFFF read.
PA_A4: PA_A4.1 Refer to PA_A3.1;
    PA_A4.2 Refer to PA_A9;

PA_Q5: Flash xxxx Manufacture Code should be 0xXX, but 0x0090 read.
PA_A5: Contact us.

PA_Q6: Pending.
PA_A6: Pending.

PA_Q7: Obsolete
PA_A7: Obsolete

PA_Q8: Pending.
PA_A8: Pending.

PA_Q9: LigthenLED() failed.
PA_A9: Troubleshooting:
    PA_A9.1 Check JTAG circuit;
    PA_A9.2 Check power supply;
    PA_A9.3 Check JTAG mode jumper settings (if any);
    PA_A9.4 Check JTAG header and connection;

PA_Q10: Pending.
PA_A10: Pending.

PA_Q11: CheckFlashID() result is not stable.
PA_A11: It happens if the board is not grounded well.

PA_Q12: Obsolete
PA_A12: Obsolete

PA_Q13: What did CheckFlashID() do?
PA_A13: The software will check Mfg ID first, and will check device ID if Mfg ID checked OK. If both Mfg and device ID (Code) are checked OK, CheckFlashID() returns successfully.

PA_Q14: Check Flash ID failed. I found WP pin is in protection mode by the software.
PA_A14: WP pin will not affect Flash ID checking.
Yes, you are right. The software will make the Flash WP pin in protection mode after initialization. The software will remove protection before writing.

PA_Q15: The JTAG device datasheet says it could support very high TCK frequency, but the software could not run as fast as that.
PA_A15: This happens when there are more than one devices in JTAG chain. You know, the working frequency depends on the lowest frequency of all devices, not the highest.

PA_Q16: The software says IDCODE mismatch.
PA_A16: First, make sure the configuration file is the right one for the board. Then check the JTAG cable and connections. Also power supply is a key point that should be reviewed.
Try to slow down TCK frequency.
If slowing down TCK frequency does not help, please check the BSDL file is matched with the device. Please note that devices in different package may use different BSDL files.

PA_Q17: Where should my u-boot.bin to program in Flash?
PA_A17: To most CPUs, the beginning address is 0. The file may have some stuffed bytes to meet the starting address.
We must declare that JFP software doesn't use any address translation module of JTAG device (CPU, for example). So it's a physical address, and it's an absolute address.
But, it does not conflict with address mapping. For example, supposed the Flash CS connected to CPU directly without address decoding, bootloader address (e.g. 0xff780000) subtracts Flash base address (e.g.  0xff000000), the result (0x780000 in this example) will be the beginning address.

PA_Q18: Pending.
PA_A18: Pending.

PA_Q19: Pending.
PA_A19: Pending.

PA_Q20: Pending.
PA_A20: Pending.

PA_Q21: How to let JFP software set the cable frequency to a given value when startup? And how to load a configuration file automatically?
PA_A21: Use a workspace file.
Note: A GUI tool called FileHelper in the software package will help you do below job since 2015/1/31.
Create a file (Edit if already existed) called yaJFPb.ini (If you are not using Boundary Scan sub-edition but other sub-edition software, please contact us), and add these lines:
;Set cable frequency to 15MHz;Change 15000000 to what you want. Read the user manual for valid values.
;Set cable clock frequency automatically when startup
;Set configuration file to d:\JFP\demo.ini
;Change 'd:\JFP\demo.ini' to any configuration file you want to load
;Note: If the configuration is in the same folder with the software, the folder info is optional.
;Load configuration file automatically when startup

PA_Q22: Pending.
PA_A22: Pending.

PA_Q23: Erase failed because the blocks are locked. But I could not unlock these blocks.
PA_A23: Try to power down the board and power up again.

PA_Q24: Will the software support Batch Programming?
PA_A24: Load corresponding workspace file, then select menu Target Device / Batch Programming in the software.
Note: A GUI tool called FileHelper in the software package will help you do below job since 2015/1/31.
Edit yaJFPb.ini File (refer to PA_Q21), and add below lines to file yaJFPb.ini:
;Split multi jobs with '|'
;Change addresses to what you expect
;Change files to what you expect
;Folder info is optional if the file is in the same folder with software.

PA_Q25: There is only ONE JTAG device on board, but the jscan software says there are multi devices, and the IDCODEs are wrong.
PA_A25: The JTAG device is a SoC that contains ARM or other CPU core(s). Usually the issue may be fixed by pulling-up or pulling-down relative configuration pins. Here are some examples:


	Example 1:
	Cortina CS8022: There are five ARM-9 embedded in CS8022. The jscan software will detect five devices.
	JTAG software will not work.
	But it's easy to handle.
	BSDL file tells us CS8022 will be in JTAG mode after changing pins (TEST_MODE_0, TEST_MODE_1, TEST_MODE_2, TEST_MODE_3, TEST_MODE_4) to (11010).
	We know from datasheet that these 5 pins have internal pull-up resistors. Remove pull-down resistors of pin TEST_MODE_0, TEST_MODE_1 and TEST_MODE_3. CS8022 will enter JTAG if requested and JFP software works happily.
	This change will not affect CS8022's normal working.


	Example 2:
	It's ST STM32F1. The jscan software will detect 2 devices: one is STM32F1, the other is ARM Cortex M.
	We just change the configure file setting to adapt this.
	Set 'Total Devices in Chain' to 2, and set 'JTAG Device Index in Chain' to 0 (Index begins with 0). We don't have BSDL file for ARM core, so we will not set BSDL file, instead we set 'Post Instruction Len' (Index of ARM is 1. ARM is behind of SM32F1) to 4.
	Now JFP and BST work.


	Example 3:
	Atmel AT91SAM9260. The jscan software will detect one device, but the IDCODE is not the one in BSDL file.
	Solution: Pull pin JTAGSEL to VDDBU, AT91SAM9260 will enter JTAG mode. JTASEL pin has internal pull-down resistor, and AT91SAM9260 will enter ICRE mode by default.
	Unfortunately, AT91SAM9260 will not work properly if JTAGSEL is pulled high, even if JTAG cable is not connected.
	So, we suggest that connect pin JTAGSEL to VDDBU with a jumper or a switch.


	Example 4:
	It's Freescale i.MX series processor. The jscan software will detect one device, but yaJFPb will report IDCODE mismatch.
	Solution: Pull pin Debug to low. The reference design writes: DEBUG=1 for ARM ETM. DEBUG=0 for boundary scan.


	Example 5:
	It's i.MX again: To i.MX6 family, the jscan software will detect 3 devices. Remove the pull-down resistor of JTAG_MOD and add a pull-up resistor for JTAG_MOD.
	Please check  if SATA and PCIe voltages are applied even if those interfaces are not used;
	Pull-down TEST_MODE pin.
	Important notice:
		Boundary scan test will fail to drive outputs on the signals: EIM_A[24:16], EIM_DA[15:0], EIM_EB[3:0], EIM_RW, EIM_WAIT and EIM_LBA. These signals can be tested as input-only.
		Please contact us for the latest software. Otherwise V2.9.2.0 or earlier version BSTest software should skip these pins, while V3.3.2.0 or earlier version yaJFPb software could not access external Flash attached to i.MX6 because of the bug of CPU.


	Example 6:
	When the jscan software detecting Qualcomm Snapdragon 820 MSM8996, three devices will be shown. Pull up MODE0 and MODE1 for boundary scan test.


	Example 7:
	To Broadcom BCM53344/BCM56260, pull up JTCE1 pin for boundary scan test.


	Example 8:
	To ST STA2165, pull up SCANEN pin for boundary scan test. TAPSEL pin will choose what device is in the chain.

PA_Q26: FTD2XX.dll not found or missing.
PA_A26: Cable driver not installed successfully. Run CDMxxxxx_Setup.exe (xxxxx stands for version number) to install driver.
PA_Q26+: After driver installed, FTD2XX.dll not found yet.
PA_A26+: Plug the USB cable to your computer to let Windows active the driver. Please read 'BSTLib Driver Install Guide'.

PA_Q27: Obsolete
PA_A27: Obsolete

PA_Q28: Is the board OK if it passes the Flash self test?
PA_A28: If the board passes the Flash self test, it means:
The configuration file is correct (including JTAG device type, Flash type, etc.);
JTAG cable works fine;
JTAG function works properly;
The circuit is OK (including address buses, data buses, chip select, read/write enable etc.);

PA_Q29: Programming will fail after some time while the Flash self test is OK.
PA_A29: Please check the reset pin of Flash to see whether Flash is reseted or not.
Secondly, please check whether other IC connected to CPU bus is affecting the bus or not.
In addition, connector issue is an uncommon cause.

PA_Q30: We noticed a new menu 'Load Workspace File' was added to V2.5.0.9. So, what's a 'Workspace File'? What's the difference between 'Configuration File' and 'Workspace File'? What doest it benefit us?
PA_A30: A 'Workspace File' specifies a 'Configuration File' and stores software settings and parameters. While a 'Configuration File' only contains board info without software settings or parameters (e.g. Programming Begin Address, Programming File, TCK Frequency, etc.)
With loading different 'Workspace File', user could switch to different workspace without manually setting relative software parameters. So, it will improve work efficiency significantly.

PA_Q31: We noticed I/O voltage of the WH-USB-HiJTAG cable is 3.3V, but VCCQ of the BPI Flash connected to my FPGA is set to 2.5V. Does it matter?
PA_A31: If your FPGA is connected with Flash properly, it does not matter. Because the cable connected to FPGA directly, and the cable will not interface with Flash I/O pins directly.

PA_Q32: What format file will be used to program Xilinx BPI Flash with yaJFPb software?
PA_A32: yaJFPb uses raw binary file.
You can convert .bit file to .bin file with Xilinx 'promgen' utility. promgen locates at %XILINX_ISE_INSTALL_FOLDER%\ISE_DS\ISE\bin\nt\ (e.g.: F:\EDA\Xilinx\12.4\ISE_DS\ISE\bin\nt\)
promgen.exe -u 0x0 button_led_test_hw.bit -p bin -data_width 16
-u 0x0: Load .bit file from starting address 0 in an upward direction.
button_led_test_hw.bit: Change it to your own bit file. Full path is required if the .bit file does not locate at current folder.
-p bin: Output file format is raw binary.
-data_width 16: BPI x16 mode.

PA_Q33: We want to integrate yaJFP software into our manufacturing automation system. How to do it?
PA_A33: You need Version or higher version of yaJFP.
Note: A GUI tool called FileHelper in the software package will help you do below job since 2015/1/31.
Add a keyword 'AutoRun' to section [Option] of yaJFPb.ini(or yaJFPs.ini, which depends on your software part number), and assign operation value to this keyword.
Supported operations: ProgramFlash() BatchProgramFlash() ReadFlashArray() Write() EraseFlashBlocks() LockFlashBlocks() UnlockFlashBlocks() LightenLED()
Multi operation should be split with character '|'.
When yaJFP starts up, all these operations will be launched one by one automatically. If no error happens, the software will quit quietly after all operations are done. Otherwise you will see a popup dialog, and the automatic processing will be halted.
Note: Correct parameters are required to be set for each operation. For parameter setting, please refer to these FAQs: PA_Q21 PA_Q24.

PA_Q34: I want to protect my Flash from being overwritten.
PA_A34: Generally speaking, you can protect boot blocks. Because the boot loader (u-boot, BIOS, etc.) will seldom be upgraded online. (If your system supports boot loader online upgrading, your upgrade firmware should unlock boot blocks before erasing and programming, and lock boot blocks when done.)
On the other hand, unless you could confirm that the Flash driver knows to unlock Flash before writing, otherwise you cloud NOT lock file system blocks, because Linux and other OS will write files when running.
Besides, you should understand:
1, The lock protection is to set a bit flag inside, it differs from the protection of WP pin. Form more info of WP pin, please refer to PA_Q14.
2, The lock protection will prevent someone from reading data out. If you need to protect the data from being copied, you should encrypt your data when programming Flash. Encrypt your file with unique ID and write unique file to each Flash on your boards.

PA_Q35: CPU boots up OK, but data read from Flash is wrong?
PA_A35: If CPU boots up and CPU leaves JTAG status while yaJFP is reading data from Flash, data presented on data bus may not be the original data in Flash at that address.
It happens when there is a watchdog which resets the CPU to boot again. Sometimes it may be caused by JTAG bug of CPU, or instability of JTAG circuit on the board.
In fact, CPU may boot successfully even if there is an error in Flash, for example, if the boot loader does not check the integrity of the ROM data and it's just an error of a text string.

PA_Q36: Why yaJFP works well on my MPC8308 board, but could not check Flash ID on Freescale's demo board?
PA_A36: The pin ball Y23 of MPC8308 should be connected to VDD (1V) to run boundary scan successfully.
After checking we found some boards, for example MPC8308 mITX REV2, Y23 is left unconnected.
When Y23 is floating, there are two issues:
1) JTAG functionality
2) RTC module does not work.
//MPC8308EC updated on 02/2011 (Rev. 2) came with this change.

PA_Q37: Does yaJFPb support MPC860?
PA_A37: Sure. And MPC860 is fully verified.
Please note: If bits 11-12 of RCW let debug pins of MPC860 work under BDM mode, you should change the mode.
If DBPC set to 01, DSCK on BDM socket now acts as TCK, DSDI as TDI, and DSDO as TDO.
TRST and TMS are not multiplexed.

PA_Q38: There is one Flash connected to CPU on board. Could we set the device type to SRAM intentionally?
PA_A38: Yes, you can set device type to SRAM even if it's a NOR Flash in fact, and you could read data from NOR flash correctly, since reading from NOR Flash and SRAM are the same.
Please note: The write method of NOR Flash differs from SRAM, so you could not write anything to NOR Flash if its device type is set to SRAM.
Also, for the same reason, the configuration file which set NOR Flash's device type to SRAM could not be used by the BSTest software for peripheral test. Because the BSTest software test SRAM with reading and writing operations, but test Flash with checking ID code.

PA_Q39: Flash self test failed, but Flash reading is OK. Why?
PA_A39: First of all, you should check whether read data is good or not. Just read some bytes from Flash and compare them with known good data.
It's because the default workspace file yaJFPb.jfp has a setting to skip Flash ID checking before reading: [Read] SkipFlashIDCheckBeforeReading is set to 1, no Flash ID checking before reading.
If reading is OK and data is correct but Flash ID checking failed, there may be something wrong with WE pin.
This may be caused by the connection between CPU and Flash, and may be caused by chip failure.
You may check waveform of WE pin at Flash side when run Flash self test, or it's better to let BSTest software generate a pattern and check the waveform at Flash pin.

PA_Q40: Why reading from Flash is much slower than writing?
PA_A40: Yes it is, especially when Flash has write buffer.
The software must do one physical hardware JTAG operation for every reading, but only do one hardware JTAG operation for multi writing since there is a write buffer.
Increase TCK frequency will speed up both reading and writing operation.

PA_Q41: What makes the difference of programming speed between yaJFPb and emulator?
PA_A41: They work in different ways.
yaJFPb works at JTAG's EXTEST mode, the core circuit of CPU is bypassed like a black box. yaJFPb generates waveforms by controlling CPU pins to operate Flash. Refer to PP_Q11.
Emulator (e.g. USB TAP) downloads code to target board's RAM with development software (e.g. Code Warrior), the CPU run programs as booted.
So, sometimes yaJFPb is faster while sometimes not, and it depends on CPU, Flash and other board configurations.
Please refer to PP_Q6, PP_Q8.
JFP Edit Cfg File FAQs

PE_Q1: How to do when address bus and data bus are multiplexed?
PE_A1: Set 'ALE (When Address & Data Bus are Multiplexed)' row to corresponding CPU pin which controls ALE of your latch.
No matter it's muxed or not, just tell the software which CPU pin is connected to each Flash pin.

PE_Q2: I don't use WP pin. How to do?
PE_A2: Left row 'WP (Write Protect)' blank.


EthCfg Pre-sales FAQs
EthCfg After-sales FAQs

EP_Q1: When multi registers were read, only value of the 1st register is correct, all values of other registers are 0xffff.
EP_A1: Please check power supply for your cable.


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The functions and features of purchased product depends on the part number and your license. | Specifications subjected to change without notice.

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